This invention relates to a circuit for generating a pulse output signal each time that an integrated circuit is energized by a source of power.
In many cases, an integrated circuit device includes logic or other circuits that must be preset or inhibited while the device is being powered up to an external power supply. A "power-up" circuit is used to generate an internal signal for presetting or inhibiting logic or other circuits and may also be used for other purposes such as triggering on-chip self-test functions. The power-up circuit must reliably detect application of voltage to the chip, whether energized rapidly or slowly.
Applications of the external power supply to a simple RC differentiating circuit might be used to perform the power-up signalling function. However, in many applications, the Vdd rise time may be on the order of milliseconds or even seconds, causing a differentiating circuit to fail to generate a pulse signal of sufficient magnitude.
The resistor of an RC differentiating circuit may be replaced by an N-channel field-effect transistor 2 switched by a Vdd trigger circuit TR of power-up circuit 3 of integrated circuit 4, as shown in FIG. 1. The trigger circuit TR that triggers the N-channel field-effect transistor 2 may be designed so that its output is low when the supply voltage Vdd is below some pre-set triggering threshold Vtr, then goes high when Vdd rises above that threshold, providing a pulse Vout at the output of the power-up circuit 3, as indicated in FIG. 2. Designing such a trigger circuit TR poses some special problems, particularly when the circuit 3 is being designed for use in a dynamic-random-access-memory (DRAM) for which the process flow is under development. Those problems result from the fact that circuit element parameters will change as the processing steps are modified during the development cycle. In particular, the trigger circuit's threshold voltage Vtr will generally vary as the circuit parameters change with process variations. Therefore, a linear trigger circuit TR must be designed for a low triggering threshold voltage Vtr because linear circuit characteristics are prone to wide variations as the process changes, requiring wide safety margins to ensure that the circuit 3 output is high at normal operating levels for supply voltage Vdd. Typical linear trigger circuits TR draw power at all times, requiring special techniques to avoid unacceptably large standby currents, particularly where such linear circuits TR have both pull-up and pull-down current paths turned on at the same time.
It is particularly difficult to design a trigger circuit TR that performs its intended function during the first part of the power-up transient when the supply voltage Vdd is below the threshold voltage Vt of the transistors in the circuit 3. While the transistors are not turned "on" in the usual sense, application of a subthreshold voltage Vdd causes normally insignificant subthreshold currents to flow from drain to source. These subthreshold currents can cause unreliable circuit 3 operation if they are not anticipated. However, the circuit 3 described herein shows how such subthreshold currents may be used to advantage. In particular, subthreshold currents may be controlled by channel length because subthreshold current has greater magnitude in short-channel devices than in long-channel devices.
When the gate-to-source voltage of a field-effect capacitor is smaller than the threshold voltage Vt, most of the gate capacitance occurs between the gate and the substrate. When the capacitor is charged to a larger voltage, most of the capacitance occurs between the gate and the source/drain, and the gate-to-substrate capacitance is insignificant. Therefore, the smaller gate-to-substrate capacitance generally dominates if the supply voltage Vdd is below the threshold voltage Vt.
Because of the above phenomena, ordinary design techniques do not apply during the initial part of the power-up switching transient in which the supply voltage Vdd is less than the threshold voltage Vt. However, the behavior of a power-up detector is critical during the initial part of the power-up transient. The behavior is particularly critical where the power-up trigger circuit TR behaves as a one-sided latch. That is, the voltage Vout at output terminal may go high and fall to ground only once while the supply voltage Vdd is high. The output voltage Vout cannot go high again until the supply voltage Vdd falls to zero and rises again, and then only if all capacitors discharge while the supply voltage Vdd is low.
Subthreshold conduction in certain elements of prior-art circuits 3 may cause the voltage Vout at the output terminal to go low when supply voltage Vdd is less than threshold voltage Vt. If this happens, the circuit might not be able to recover. Some prior-art circuits have been designed with feedback to hold the output terminal low once it has gone low. In these circuits 3, the feedback path may turn on even before supply voltage Vdd reaches threshold voltage Vt if the voltage across certain elements goes high prematurely. This makes it critically important for the power-up trigger circuit TR to be absolutely reliable, even in the range where usual design techniques do not apply.
In particular, the outputs of usual logic gates are unpredictable during the part of the power-up transient in which supply voltage Vdd is less than the threshold voltage Vt. Since normal gates have both pull-up and pull-down capabilities, their outputs may go either high or low when supply voltage Vdd is less than threshold voltage Vt, and the states on the gate inputs may not control the outputs. Therefore, it is especially risky to use common logic gates for Vdd detectors.
One of the problems with use of such common logic gates is that both pull-up and pull-down gates may be caused to be on at the same time, forming a linear circuit of the type mentioned above. Therefore, a logic gate may have the same problems as a linear circuit during the power-up transient.
Another problem is an unacceptable amount of standby current drawn by a linear power-up circuit 3. Use of a detector circuit with a dynamic pull-up rather than a static pull-up to solve this problem has been shown to provide an unreliable signal on second start-up occurring shortly after a first start-up. Use of static inverters in feedback paths has also resulted in unpredictable behavior when supply voltage Vdd is below threshold voltage Vt because the feedback path turns on prematurely, causing the trigger circuit TR to fail.
Examples of prior-art circuits 3 for generating a "power-up" pulse are illustrated in U.S. Pat. No. 4,716,322 and in U.S. patent application Ser. No. 07/172,532 filed Mar. 24, 1988 (now U.S. Pat. No. 4,888,498), both of which are assigned to Texas Instruments Incorporated.
In the circuit of U.S. patent application Ser. No. 07/172,532, a P-channel capacitor assisted by a P-channel pull-up transistor acts to cause the output signal of the power-up circuit 3 go high. A linear circuit comprising a P-channel transistor and a string of N-channel transistors forms the trigger circuit TR. As the supply voltage Vdd rises, the voltage output rises with Vdd until the trigger circuit output rises to threshold voltage Vt. After that, the output voltage Vout is pulled low by the N-channel pull-down transistor gated by the trigger circuit output. When the output voltage Vout goes low, the N-channel transistor string is turned off to save power and a P-channel feedback device is turned on to hold the output high. Because the trigger circuit TR is a linear circuit, its threshold voltage Vout is prone to be sensitive to process variations. In addition, the N-channel device that turns off the N-channel transistor string, in combination with the P-channel feedback device, forms a circuit that resembles a static inverter, which may perform unpredictability when the supply voltage Vdd is less than the threshold voltage Vt. Another problem is that noise in the supply voltage Vdd, caused by an external clock cycling, may tend to turn off the trigger circuit TR prematurely.